1. Field of the Invention
The present invention relates generally to a ramp signal generation circuit, and more particularly, to a ramp signal generation circuit incorporated in a complementary metal-oxide-semiconductor (CMOS) image sensor.
A claim of priority is made to Korean Patent Application No. 2004-6121, filed Jan. 30, 2004, the disclosure of which is incorporated herein by reference in its entirety.
2. Description of the Related Art
A CMOS image sensor (CIS) typically operates at a lower voltage than a charge-coupled device (CCD), has lower power consumption, can be manufactured more efficiently by a employing standard CMOS fabrication process, and allows other processes to be readily integrated on the CMOS chip along with the image sensor. For at least these reasons, it is expected that CISs will take the place of CCDs in many imaging devices in the future.
Unlike a CCD, however, a CIS requires a high resolution Analog-to-Digital Converter (ADC) to convert analog signals output by an Active Pixel Sensor (APS) into digital signals.
At least two methods exist for converting analog signals into digital signals in a CIS. One common method uses a single ADC while another method uses a column ADC. The method that uses a single ADC converts analog signals output by several columns of APS units into digital signals in a predetermined time interval, using a single ADC operating at a high speed. Accordingly, the surface area required to mount the ADC on a semiconductor chip is small. However, the CIS power consumption is relatively high since the single ADC typically operates at a high speed.
In the method using the column ADC, a single ADC having a relatively simple structure is typically allocated for each APS unit. The resulting CIS power consumption is lower than in the foregoing approach, but the chip area occupied by the ADCs is relatively large. In a CIS using a column ADC, one unit block of the image sensor (i.e. a block corresponding to a single pixel) comprises a ramp signal generation circuit and a comparator. Any attempt to simultaneously address the issues of performance, size, and power consumption by emerging CIS structures necessarily implicates the design and performance of the ramp signal generation circuit and comparator.